The present invention relates to a technology for controlling cache in multiprocessor machines. More specifically, the present invention relates to cache controller in chip multiprocessors.
An example of a conventional technology for controlling multiprocessor cache is a technology that seeks to increase speed by reducing control hardware and control signal traffic from control data used to maintain consistency in data shared between the plurality of processors. Examples of this technology are described in Japanese laid-open patent publication number Hei 11-272557, Japanese laid-open patent publication number Hei 09-293060, and Japanese laid-open patent publication number Hei 08-263374.
With LSI chips, the data transfer between the chip and external components is restricted by the physical limitation of the number of chip pins. Thus, it would be desirable to reduce the communication between the chip and external components as much as possible. Thus, with chip multiprocessors in which two or more processors and a cache are integrated on an LSI chip, cache control must be performed to reduce the communication between the on-chip cache and external components.
In the conventional technology described above, the communication between the chip and external components cannot be reduced. On the other hand, the object of the conventional technology to simplify and increase the speed of control performed to maintain cache consistency is not a major issue since a large amount of data can be communicated between the on-chip processors.